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Integration of III-V and IV-IV heterostructures on silicon by direct epitaxy using crystalline oxide buffers




Crystalline oxid

Statut des brevets

French patent application FR0757652 filed on September 18th, 2007.


Philippe REGRENY


Institut des nanotechnologies de Lyon (INL)


The diversification of the materials used in Si-based microelectronic technologies is the only way to overcome the intrinsic limitations of standard CMOS devices. In particular, finding solutions to integrate III-V based light emitters and detectors with Si-based CMOS circuits, or to integrate high mobility Ge or III-V channels would allow major improvement of the device performances. Defining a monolithic process is particularly relevant in terms of reliability and technological costs, and is required for full wafer technologies and solar cells applications.

The monolithic solution proposed here is original and liable to come off the definition of a process that fulfils the abovementioned requirements.


The invention consists in using crystalline oxide buffers grown by ultravacuum or vapour deposition techniques on Silicon to regrow Ge and various III-V alloys. The crystallographic and chemical symmetry breaking at the heterointerface between crystalline oxides such as (Ba,Sr)TiO3, Gd2O3, Al2O3 (that can be grown on Si) and the Ge or III-V semiconductors leads to very interesting properties. In particular, Ge and III-V grow with their bulk lattice parameter on these oxide buffers, which allows avoiding the formation of threading defects as in the case where they are directly grown on Si. Thus, high quality Ge and III-V heterostructures could be monolithically integrated on Silicon if the process is fully controlled, independently of the lattice mismatch.

To achieve this goal, a major issue consists in controlling the very beginning of the growth of the semiconductor on the crystalline oxide buffer. We have developed a specific process that enhances the wetting and thus allows obtaining flat semiconductor layers having their bulk lattice parameter on oxide/Si buffers. These layers are free of extended defects related to any plastic relaxation mechanism despite the large lattice mismatch.

The most promising feature of our process relies in its universality in terms of material systems : on the contrary to what is observed for standard heteroepitaxial processes, the lattice mismatch has no direct influence on the formation of defects in the layers in the framework of our technology. We have up to now mostly focused our efforts on the monolithic integration of InP, Ge and GaAs on (Ba,Sr)TiO3/Si(001) and Gd2O3/Si(111) crystalline buffers, but there is no reason why other semiconductors such as InAs or large bandgap III-N alloys cannot be grown on these buffers using our technology.


  • – Universal « compliant » buffer for the monolithic integration of various semiconductors on Si
    – Compliance occurs spontaneously without any surface technological treatment or patterning
    – Full wafer technology : III-V layers can be monolithically integrated on large size Si basewafers
    – Low cost (monolithic technology)


– Microelectronics, heterogeneous integration

– Solar cells

– Production of large size « pseudosubstrates » for semiconductor industry


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  • Ce champ n’est utilisé qu’à des fins de validation et devrait rester inchangé.

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