In the last few years, it has been proposed a new method for reconfiguring partially a FPGA. This method is well known as partial and dynamic FPGA reconfiguration from Virtex (Xilinx).

The goal is to configure partially the FPGA for each kind of function that must be run. Therefore the silicon size of the FPGA is considerably decreased, as there is no need to implement all functions that could one day be used.

However, this method implies to memorize the reconfiguration data for all applications that can be run on the FPGA.

Then, the silicon area won in the FPGA is wasted by memories.

TECHNICAL DESCRIPTION

The invention allows partial dynamic reconfiguration of a FPGA connected to a network. Configuration data are loaded into the memory resource of the FPGA via a server connected to the network.

The invention is based on the access to a server containing the configuration data in data link layer (the layer 2 of the OSI model) via a local network.

The server is connected to the same network as the FPGA. It is unneeded to implement a routing system in the network layer (third layer of the OSI model)

Then, the invention provides an easy and low cost method to configure dynamically and partially a FPGA.

BENEFIT

Low cost
Reduction of memory resources
Easy to reconfigure

INDUSTRIAL APPLICATIONS

Digital Signal, Image Processing and Multimedia applications, embedded applications for system on chip design, 3 and 4G telecom applications: the end users portable device becomes field-adaptable by downloading software and configware (for the reconfigurable core) over the network down to the customer location: for instance for bug fixes, updates for changes (protocols and others), upgrading for new services (e. g. for innovating network services), adaptation to environments, or regional mobile phone standards (multi-standard handles).

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