CONTEXT

The conventional 1-Transistor+1-Capacitor DRAM is extensively used in the semiconductor industry for manufacturing high density dynamic memories. Beyond the 45nm node, the DRAM industry will need new concepts avoiding the miniaturization issue of the memory-cell capacitor. The most attractive solution is to suppress the storage capacitor and use the floating body of SOI transistors to store the charge. Several 1T-DRAM devices have been already proposed, but they are difficult to scale due to the thick body needed for the coexistence of electrons and holes. The patent proposed here introduces a totally novel 1T-DRAM memory device based on the coupling of majority and minority carriers in highly-scaled Fully Depleted Silicon On Insulator transistors (FD-SOI)

TECHNICAL DESCRIPTION

The advanced-RAM (A-RAM) architecture is compatible with single-gate SOI, double-gate, FinFETs and multiple-gate FETs (MuFETs).

The A-RAM features absolutely original architecture and operation which enable the physical separation of majority and minority carriers. State « 1 » is defined by the presence of majority carriers which leads, via electrostatic coupling, to the formation of a minority carrier channel. State « 0 » corresponds to the absence of such a channel. The unique architecture is compatible with deep scaling. The advantages of the A-RAM device are: single-gate operation (no mandatory need for back gate biasing), easy discrimination of a « 1 » and « 0 » states, low power consumption, and simple programming and reading. Numerical simulations have demonstrated competitive programming and retention times which result from the separation of the two types of carriers. In addition, A-RAM can be combined with double/multiple-gate FETs, introducing a new paradigm in DRAM technology: multiple bit memory in a single transistor.

BENEFITS

Performance/Price
A-RAM concept is in between SRAM and DRAM: no refreshing is needed after reading the information and high operation speed has been proved, while keeping only one transistor per cell. Once the technology would be full optimized, it could offer leading performance. The price is DRAM like.

Read and Write cycle time
From simulations, writing is achieved in less than 10ns. Scaling the device, and after optimization this number can be reduced. Reading is just the time needed to measure a current (not limited intrinsically by the memory cell).

Volatility
The information is volatile, but reading is a non-destructive process, the storage state is not affected by reading the information. The retention time is being optimizing now, at least seconds.

Soft Error Rate
A-RAM is intrinsically a SOI structure, with ULTRATHIN active regions (works on Fully Depleted SOI) so therefore mitigating radiation effects.

Density
1 transistor per cell.

Voltage
Ultra low, this is one of our big points. No bias for reading. No charging capacitors. Speed Grade. Leading edge reading, writing in ns range.

RoHS Compliant
Status of development. Supported by simulations, scientist work now on optimization.