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MS-DRAM Processing and methods for a new type of floating-body, capacitor-less 1T-DRAM

Référence

02020-01

Statut des brevets

Priority patent application US prov 61/006280 filed on January 4th, 2008

Inventeurs

Sorin CRISTOLOVEANU
Maryline BAWEDIN
Denis FLANDRE
Christian RENAUX
André CRAHAY

Statut commercial

Exclusive or non-exclusive licenses

Laboratoire

IMEP, France, http://imep-lahc.grenoble-inp.fr/
UCL, Belgique, http://www.uclouvain.be/en-index.html

Description

CONTEXT

The semiconductor market aims at decreasing the device size while reducing the power consumption and increasing the speed. Silicon-on-Insulator (SOI) technology is one of the most promising candidates which features unique characteristics particularly well suited to achieve such performances.

Within this general context, new types of capacitorless DRAMs using a single SOI transistor, the 1T-DRAM, are recently attracting interest.

TECHNICAL DESCRIPTION

The patent proposed here describes an innovative memory cell concept, based on the MSD effect (Meta-Stable Dip) and named MSDRAM (Meta-Stable DRAM). The MSDRAM was developed at the UCL and investigated in collaboration with the IMEP laboratory (INPG, France).

The MSDRAM is dedicated to multiple-gate SOI technology which is expected to be included in future CMOS generations comprising devices such as double-gate transistors, FinFETs and multiple-gate FETs (MuGFETs). The MSDRAM is totally original and takes advantage of the double-gate operation in fully depleted SOI. One gate is used to adjust the body potential and the other gate reads the corresponding current values in “0” and “1” states. The MSDRAM displays improved performances such as the retention time and “0”-state current level. Furthermore, with our specific memory array configuration and operation, the programming time and voltage are competitive leading to significant reduction in power consumption. Experimental results are available for long-channel MSDRAMs. More importantly, the device is aggressively scalable as demonstrated by numerical simulations down to 50 nm gate length. The present invention deals with two directions which significantly improve the performances through specific technological process and array implementation of such devices. Practical examples of implementation schemes and dedicated technological steps are given. Other solutions are available for discussion. In comparison with other memories using only one transistor, the MSDRAM exploits the full depletion and double-gate action (for enhanced scaling capability). This results in very long retention time, high current ratio between “0” and “1” states, and low-power consumption. The MSDRAM can serve for embedded or standalone high density memories

BENEFITS

– small area
– low-power consumption
– long retention time
– scalability

For further information, please contact us (Ref 02020-01)


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